DZIF=0, QIF=0, N=0, Q=0, V=0, VIF=0, DZ=0
CSR Interrupt Flags Clearance Register
| Q | Q flag: Accumulation Overflow 0 (0): Write “0” will clear CSR[Q] 1 (1): Write “1” will set CSR[Q] |
| V | V flag: Multiply or Divide overflow 0 (0): Write “0” will clear CSR[V] 1 (1): Write “1” will set CSR[V] |
| DZ | DZ flag: Divide by Zero 0 (0): Write “0” will clear CSR[DZ] 1 (1): Write “1” will set CSR[DZ] |
| N | N flag: Signed calculation result is negative 0 (0): Write “0” to clear CSR[N] 1 (1): Write “1” to set CSR[N] |
| QIF | Q Interrupt Flag: Accumulation Overflow Interrupt Status 0 (0): Write “0” is ignored 1 (1): Write “1” to clear CSR[QIF] |
| VIF | V Interrupt Flag: Multiply or Divide overflow 0 (0): Write “0” is ignored 1 (1): Write “1” to clear CSR[VIF] |
| DZIF | DZ Interrupt Flag: Divide by Zero 0 (0): Write “0” is ignored 1 (1): Write “1” to clear CSR[DZIF] |